FIG. 1 shows a plurality of communication channels 14(x) for communicating data between a first device 10 and a second device 12. In one embodiment the devices 10 and 12 can comprise discrete integrated circuits, such as a Synchronous Dynamic Random Access Memory (SDRAM) and a microprocessor in one example. In this example, communication channels 14(x) would typically comprise traces in a printed circuit board (PCB) 15. Alternatively, devices 10 and 12 could comprise circuit blocks on a common substrate, with channels 14(x) comprising traces on the substrate.
The communication channels 14(x) as illustrated are bidirectional, allowing data to be sent from device 10 to device 12 and vice versa. When data is sent from device 10 to device 12, the transmitters TX are activated in device 10 and the receivers RX are activated in device 12. Likewise, when data is sent from device 12 to device 10, the transmitters TX are activated in device 12 and the receivers RX are activated in device 10.
As shown, each of the illustrated communication channels 14(x) are “single-ended,” meaning that the transferred data only appears at one point in a given receiver, RX. By contrast, other communication channels in the art are differential, meaning that data and its complement are transferred on two traces, with both the true and complement data values being received at a differential receiver. See, e.g., U.S. patent application Ser. No. 11/972,209, filed Jan. 10, 2008.
The received data at each receiver RX, typically implemented as amplifiers, is compared to a reference voltage, Vref. As is well known in such single-ended applications, Vref comprises a threshold, such that data having a higher voltage than Vref is interpreted by the receiver RX as a logic ‘1’, while data having a lower voltage than Vref is interpreted as a logic ‘0’. Because Vref is essentially a constant voltage, the comparison of the data and Vref at the receivers is sometimes known in the art as a “pseudo differential” approach, owing to the fact the Vref is a mere threshold voltage, rather than a data complement.
Limited pin count, lower power, and the availability of legacy design work motivate the effort to increase the bandwidth of, and hence prolong the life of, single-ended signaling. While most single-ended signaling innovation targets either noise reduction through encoding techniques and supply insensitive circuit design, or bandwidth enhancement through equalization, little focus has apparently been given to techniques for reference voltage (Vref) generation, an important parameter that impacts the voltage and timing margins of the communication channels.
Vref generation became a requirement of early DDR (Double Data Rate) SDRAM standards, which specified that the Vref generator 16 comprise a simple resistor-based voltage divider (with Vref at its center point) placed on the PCB 15, as shown in FIG. 1, such that:Vref=(Rb IRa+Rb)*Vddq=m*Vddq  (Eq. 1)where m is a scaling factor comprising the Vref voltage level relative to Vddq. As this term captures the relative nature of Vref and Vddq, it may also be seen as a “slope” or rate of change in Vref versus a corresponding rate of change in Vddq. Vref, so generated, was then distributed to all necessary components, including the receivers, RX, in the devices 10 and 12. This voltage divider in earlier years was configured to generate a DC reference midway between V ddq and Vssq (i.e., Ra=Rb, or m=0.5), where Vddq and Vssq are the I/O power supplies for the devices 10 and 12. As one skilled in the art will understand, often the I/O power supplies Vddq and Vssq are isolated from the corresponding power supplies Vdd and Vss used internal to the devices 10 and 12. Driving the power domains in this manner help to keep noise in the communication channels 14(x) from affecting internal signaling such as internal transmitted and received data signals DXx and DRx, which is referenced to the Vdd/Vss domain. See, e.g., U.S. patent application Ser. No. 12/208,562, filed Sep. 11, 2008.
Eventually, DDR SDRAM technology migrated to the use of Vddq-referenced signaling, in which logic ‘1’ and ‘0’ are referenced to Vddq, such that a logic ‘1’ equals Vddq, and a logic ‘0’ equals a voltage between Vddq and Vssq, but may not equal Vssq. (Vssq-referenced signaling would be similar in that a logic ‘0’ equals Vssq, while a logic ‘1’ equals a voltage between Vddq and Vssq, but may not equal Vddq). Such changes precipitated changes to Vref generation. First, the option of generating Vref internal to the receiving device 10 or 12 was introduced, which simplified system design, and removed the requirement of external Vref pins on the devices 10 or 12. Second, due to the fact that Vddq-referenced signaling might not produce signals with a midpoint voltage between Vddq and Vssq, the internal Vref generator 20 was designed to be capable of tuning the Vref level, such as is shown in FIG. 2. Vref generator 20 comprises a series connection of resistors Ra1-RaN between Vddq and Vref, and a series connection of resistors Rb1-RbN between Vref and Vssq. As shown, any of these resistors can be bypassed through digital control (Ta1-TaN; Tb1-TbN) to arrive at tunable values for Ra and Rb per Equation 1 above. Such tunability allowed Vref to be trained to maximize voltage and/or timing margins during channel initialization.
Optimal Vref generation in Vddq-referenced signaling preferably takes into account the relationship between transmitter TX's pull-down or pull-up drive strength and the receiver RX's on-die termination (ODT) resistance, which are shown in FIG. 3. As shown, Rpu and Rpd respectively represent the pull-up and pull-down resistances at the transmitter, while Rodt represents the receiver's resistive on-die termination to Vddq. When sending a logic ‘1’, Rpd is effectively removed from the network, and both ends of the channel 14 are brought to the same potential (Vddq). In other words, the voltage of a transmitted logic ‘1’ at the receiver, Vhigh, equals Vddq.
Conversely, when sending a logic ‘0’, Rpu is removed from the network, and Rodt, the channel 14 resistance (not shown and ignored), and Rpd are connected in series between Vddq and Vssq. This voltage divider sets the voltage of a transmitted logic ‘0’ at the receiver, Vlow, which equals Vlow=(Rpd/(Rpd+Rodt))*Vddq (assuming Vssq=0V).
From this analysis, it would appear that the optimal value for Vref would be exactly one-half of the way between Vhigh and Vlow:Vref=(Rpd+0.5Rodt)/(Rpd+Rodt)*Vddq.  (Eq. 2)However, this optimal value for Vref can be misleading in a realistic communication channel, which will suffer from non-idealities such as simultaneous switching output (SSO) noise, inter-symbol interference (ISI), crosstalk, and duty-cycle distortion (DCD). All of these effects combine to distort the data presented to the receiver, RX, and thus effect the level of Vref that would be optimal for a given system.
DCD in particular, which can result from pull-up/pull-down asymmetry at the transmitter and/or from a distorted data strobe, can severely alter the shape of the received data “eye,” as shown in FIG. 4. (The concept of statistically analyzing data from the perspective of a data eye is well known, and is discussed further in U.S. patent application Ser. No. 11/930,524, filed Oct. 31, 2007). As one skilled in the art understands, a data eye represents a statistical picture of data reception for a given communication channel, and the internal region of the eye represents the region in which data can be accurately sensed from both a voltage margin and a timing margin perspective. A reliable communication channel would thus preferably be characterized by a data eye that is as “open” as possible, as this would maximize the margins at which the data could be sensed.
FIG. 4 shows hypothetical data eyes for a Vddq-referenced system. The first data eye shows the data integrity at a first Vddq value of 1.0V. At this level, a satisfactory and symmetrical data eye results. The maximum voltage for the eye, Vhigh, equals Vddq (1.0V) as discussed earlier. The minimum voltage, Vlow, equals some value between Vddq and Vssq, and is shown as 0.5V here for illustrative purposes. (Per the equations discussed above with respect to FIG. 3, Vlow=0.5 would be consistent, for example, in a system having a transmitter, TX, having pull-up and pull-down resistances, Rpu and Rpd, of 50Ω, transmitting into a 50Ω termination resistance (Rodt) relative to a 1V VDDQ). To accommodate such Vddq-referenced signaling, a tunable Vref voltage is desirable, and the level for Vref would logically be set to the middle of the Vhigh and Vlow values, such that, in this example, Vref=0.75*Vddq, or 0.75 V (assuming Vssq=0V). The tunable Vref generator 20 used to set this Vref value is shown at the bottom of FIG. 4, and comprises the voltage divider of Equation 1, with Rb=3*Ra, which establishes a slope m=0.75, per Equation 1.
The second data eye shows the system in the case that Vddq has degraded from 1.0V to 0.9V, which degradation could be permanent or transient. In this example, it is assumed that the P-channel devices in the transmitters TX will begin to lose their drive strength at low voltages, resulting in a distorted eye which is biased toward lower voltages and which decreases the sensing margin of the logic ‘1’ state. Because Vhigh, Vref, and Vlow each scale with Vddq, it can be seen that these values shift accordingly to 0.9V, 0.675V, and 0.45V, respectively.
However, due to the asymmetry of the degraded eye, the designated Vref voltage of 0.675V may not be optimal, and it might be preferable in this example to shift Vref downward to better center Vref nearer to the centroid of the area encompassed by the eye (e.g., at Vref′=0.67). Because the eye is wider at this Vref′ point, the timing margins are improved, and sensing is eased at the receivers.
However, because the Vref generator 20 only allows Vref to scale with Vddq in accordance with a given slope m, per Equation 1 above, Vref generator 20 simply won't allow Vref to be optimized for both the non-degraded and degraded cases. This could impede the sensing operation in either of these cases, and thus presents a shortcoming in the design of the Vref generator 20.
The inventor has realized that providing such optimization of Vref requires the use of a generator in which both the Vref-to-Vddq slope m, and its offset or intercept b, can be independently varied, and embodiments of such a Vref generator are provided in this disclosure.